1. Field of the Invention
The present invention relates to a semiconductor memory device which can suppress an operation error arising from power supply noise and, more particularly, to a semiconductor memory device which incorporates an address transition detector (ATD) and hence realizes a high-speed operation.
2. Description of the Related Art
An ATD is incorporated in a memory device in order to realize high-speed reading of memory data of a semiconductor memory device. The ATD detects a change in address signal and generates a clock pulse. The clock pulse generated from the ATD is used for equalizing control of bit and sense amplifier lines, and the like, so that a high-speed reading operation can be realized. More specifically, before an address is selected in accordance with the change in address signal, the potentials of a pair of bit lines and a pair of sense amplifier lines arranged at an output terminal of a sense amplifier are equalized on the basis of the control, in response to a clock pulse generated from the ATD. Therefore, the influence of a data output during a prior cycle is erased in a short period of time.
The ATD is described in, for example, 1987 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 264, 265 and 420 "A 25ns 1Mb CMOS SRAM" T.Ohtani et. al., 1985 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 64, 65 and 306 "A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier" Kiyofumi Ochii et. al., 1984 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 216, 217 and 341 "A 30ns 64K CMOS RAM" Kim Hardee et. al., and the like.
In a memory device having a memory designed for high-speed operation, in particular, a memory device having a large number of data bits, i.e., one having an output configuration of 8-bits or more, power supply noise is generated due to a large peak current when a data output buffer is driven, and internal circuits are erroneously operated. The operation error is exemplified by a detection error of an input signal level caused by power supply noise. When a power supply potential is varied due to a large driving current during an operation of the output buffer, the detection error is caused. The change in power supply potential is conducted to an address input buffer by distributed parasitic inductance and distributed parasitic resistance in a power supply line. Therefore, the detection level of the address input buffer is changed, and hence an erroneous address input signal is supplied to a decoder. For this reason, the memory cell at an erroneous address is selected, and memory data of the memory cell is output. If the power supply noise is significantly increased and the above phenomena are repeated, a chip mounting the memory devices is often set in the oscillation state.